Network-on-Chip (NoC) is an interconnect infrastructure in modern many-core and multi-core architectures. Other interconnect infrastructures are buses and crossbars. General-purpose systems with a small number of cores (i.e., 4 core processors) may perform better with buses and crossbars, but the cost to performance ratio starts decreasing with an increase in the number of cores. Performance is usually measured in latency and throughput, where cost is measured in power consumption and physical area on the chip.

There are five building blocks of an NoC.

1. Topology
2. Routing Algorithm
3. Flow Control Mechanism
4. Router Microarchitecture
5. Link Architecture

The topology is the physical layout of the interconnection of router nodes. For example, router nodes can be connected in a mesh (4×4). The routing algorithm decides the direction of messages. For example, in a mesh topology NoC, a message will go right, left, up, or down. The flow control mechanism decides the granularity of the allocation of physical NoC resources for network traffic. A common granularity is flit level, where a message is divided into flits. The router microarchitecture is the implementation of a routing algorithm, and flow control mechanism. A generic microarchitecture of NoC is consists of buffers (at input), a switch (also called crossbar), routing logic and router states, and allocators. The link architecture decides how two neighbor nodes are connected to each other. Pipelined wires are examples of link architectures.